At present, in current base station technologies of wireless communications, a received analog signal needs to be converted to a digital signal, and then operation processing is performed in the digital domain to implement various functions and achieve the objective of information transmission. An analog digital converter (ADC) discretizes an analog signal in terms of time and amplitude to convert the analog signal to a digital signal. Such devices are the most commonly used devices in existing analog and digital hybrid systems.
Existing ADC architectures are relatively commonly used digital interfaces with ADC parallel output, mostly in two forms. One form is that each converter core (ADC core) corresponds to one direct output interface, referring to FIG. 1, leading to numerous interfaces when multiple converters are used, which imposes pressure onto implementation of a backend field-programmable gate array (FPGA) or application specific integrated circuit (ASIC).
A second form is that multiple converters correspond to one interface, and a multi-selector is used to output multiple ADC core output signals by means of time division multiplexing, referring to in FIG. 2. However, processing data by means of time division multiplexing does not reduce the throughput of an interface. Moreover, in existing communications systems or other ADC-equipped sampling systems, to avoid aliasing of digital signals, an actually used bandwidth is narrower than an actual Nyquist bandwidth, and therefore, there is much unnecessary information in the signals output by the interfaces. This part of information also occupies a substantial portion of the processing bandwidth of an interface.